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KT0806L monolithic digital stereo fm transmitter radio-station-on-a-chip? ? features hardware compatible with kt0806 additional features to kt0806 software standby; automatic power down power amplifier when silence is detected; multiple reference clock support including from 32.768khz to 26mhz; alc (automatic level control) higher snr (66db) increased audio frequency response software controlled xtal selection professional grade performance: snr 66 db stereo separation > 40 db international compatible 70mhz ~ 108mhz ultra-low power consumption: < 17 ma operation current < 3 a standby current small form factor: 16-pins qfn 3x3 simple interface: single power supply standard 2-wire i 2 c mcu interface advanced digital audio signal processing: on-chip 20-bit ? audio adc on-chip dsp core on-chip 24db pga with optional 1db step automatic calibration against process and temperature 1.6v ~ 3.6v supply programmable transmit level programmable pre-emphasis (50/75 s) pb-free and rohs compliant applications mp3 player, cellular phone, pda, pnd, portable personal media player and its accessory, laptop computer, wireless speaker rev. 1.4 information furnished by kt micro is believed to be accurate and reliable. however, no responsibility is assumed by kt micro for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of kt micro, inc.. figure 1: KT0806L system diagram ? general description KT0806L, our new generation of low cost monolithic digital fm transmitter, is designed to process high-fidelity stereo audio signal and transmit modulated fm signal over a short range. it?s based on the architecture of award- winning kt0801 and it?s also an upgrade of kt0806. the additional features added to KT0806L are standby mode through software, alc (automatic level control), multiple reference clock, increased snr performance and frequency response. the KT0806L features dual 20-bit ? audio adcs, a high- fidelity digital stereo audio pr ocessor and a fully integrated radio frequency (rf) transmitter. an on-chip low-drop-out regulator (ldo) allows the chip to be integrated in a wide range of low-voltage battery-operated systems with power supply ranging from 1.6v to 3.6v. the KT0806L is configured as an i 2 c slave and programmed through the indust ry standard 2-wire mcu interface. thanks to its high integration level, the KT0806L is mounted in a generic 16-pin qfn package. it only requires a single low-voltage supply. no external tuning is required that makes design-in effort minimum. kt micro, inc., 22391 gilberto, suite d rancho santa margarita, ca 92688 tel: 949.713.4000 http://www.ktmicro.com fax: 949.713.4004 copyright ? 2010, kt micro, inc. .
copyright ? 2010, kt micro, inc. 2 KT0806L 1 operation condition table 1: operation condition parameter symbol operating condition min typ max units io/regulator supply iovdd relative to gnd 1.6 3.6 v ambient temperature t a -30 25 70 2 specifications and features table 2: fm transmitter functional parameters (unless otherwise noted t a = -30-70 , iovdd=1.6~3.6 v, f in = 1 khz) parameter symbol test/operating condition min nom max units fm frequency range f tx pin 12 70 108 mhz current consumption i vdd pin 16 with pa (power amp.) at default power mode (pa_bias = 0, rfgain[3:0]=1111) - 17 ma standby current i stand pin 16 - 0.1 1 a signal to noise ratio snr v in = 1 v p-p , g in = 0 - 66 - db total harmonic distortion thd v in = 1 v p-p , g in = 0 - 0.3 % left/right channel balance bal v in = 1 v p-p , g in = 0 -0.2 - 0.2 db stereo separation (left<->right) sep v in = 1 v p-p , g in = 0 40 - db sub carrier rejection ratio scr v in = 1 v p-p , g in = 0 - - 60 db input swing 1 v in single-ended input - 0.35 2 v rms pga range for audio input g in -15 0 12 db pga gain step for audio input g step 1 4 db required input common-mode voltage when dc-coupled v cm pin 2,4 0 0.8 1.8 v power supply rejection 2 psrr iovdd = 1.9 ~ 3.6 v 40 - - db ground bounce rejection 2 gsrr iovdd = 1.9 ~ 3.6 v 40 - - db input resistance (audio input) r in pin 2, 4 120 150 180 k ? input capacitance (audio input) c in pin 2, 4 0.5 0.8 1.2 pf audio input frequency band f in pin 2, 4 20 - 15k hz transmit level v out 96 103 113 dbv channel step step - 50 khz pilot deviation 7.5 15 khz audio deviation 75 112.5 khz frequency response mono,-3db, f=60khz, 50/75 s pre-emphasis 20 15,000 hz phtcnst = 1 - 50 - s pre-emphasis time constant t pre phtcnst = 0 - 75 - s crystal/external clock clk input clock 32.768 40,000 khz 2-wire i 2 c clock scl pin 11 0 100 400 khz high level input voltage v ih pin 7, 8, 10, 11 0.75 x iovdd - iovdd + 0.25 v low level input voltage v il pin 7, 8, 10, 11 - 0.25 - 0.25 x iovdd v notes: 1. maximum is given on the condition of pga gain = -15db. 2. fin = 20 ~ 15khz.
copyright ? 2010, kt micro, inc. 3 KT0806L 3 package and pin list table 3: KT0806L pin definition pin index name i/o type function 1 nc not connected internally. 2 inl analog input left channel audio input. 3 gnd ground ground. 4 inr analog input right channel audio input. 5 nc1 reserved. do not connect. 6 nc2 reserved. do not connect. 7 sw1 digital input control bit. chip enable, supply mode and clock source. 8 sw2 digital input control bit. chip enable, supply mode and clock source. 9 gnd ground ground 10 sda digital i/o serial data i/o. 11 scl digital i/o serial clock input. 12 pa_out analog output fm rf output. 13 gnd ground ground 14 xo analog i/o crystal output. 15 xi/clk analog i/o crystal input or external reference clock input. 16 iovdd power 1.6~3.3v external logic iovdd or regulator high supply input. figure 2: pin-out 1 2 3 4 5 6 7 8 12 11 10 9 16 15 14 13 nc inl gnd inr pa_out scl sda gnd gnd xo xi/clk iovdd top view sw2 sw1 nc2 nc 1
copyright ? 2010, kt micro, inc. 4 KT0806L 4 i2c compatible 2-wi re serial interface 4.1 general descriptions the serial interface consists of a serial controller and registers. an internal address decoder transfers the content of the data into appropriate registers. please note that the i2c address is 0x 0110110 the same as in kt0806. neither software nor hardware change is needed if KT0806L is used to replace kt0806. both the write and read operations are supported according to the following protocol: write operations: byte write: the write operation is accomplished via a 3-byte sequence: serial address with write command register address register data a write operation requires an 8-bit register address following the device address word and acknowledgment. upon receipt of this address, the KT0806L will again respond with a ?0? and then clock in the 8-bit register data. following receipt of the 8-bit register data, the KT0806L will output a ?0? and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition (see figure 3). read operations: random read: the read operation is accomplished via a 4-byte sequence: serial address with write command register address serial address with read command register data once the device address and register address are clocked in and acknowledged by the KT0806L, the microcontroller must generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. the KT0806L acknowledges the device address and serially clocks out the register data. the microcontroller does not respond with a ?0? but does generate a following stop condition (see figure 3). random register write procedure s 0 1 1 0 1 1 0 w a a ap 7 bit address register address data acknowledge acknowledge stop condition start condition write command acknowledge random register read procedure s 0 1 1 0 1 1 0 w a as0111110 r a a p 7 bit address register address 7 bit address data acknowledge acknowledge acknowledge start condition write command read condition no acknowledge stop condition figure 3: serial interface protocol
copyright ? 2010, kt micro, inc. 5 KT0806L current address read: the internal data register address counter maintains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. once the device address with the read/write select bit set to ?1? is clocked in and acknowledged by the KT0806L, the current address data word is serially clocked out. the microcontroller does not respond with an input ?0? but does generate a following stop condition (see figure 4). current register read procedure s 0 1 1 0 1 1 0 r a a p 7 bit address data acknowledge stop condition start condition read command no acknowledge figure 4: serial interface protocol note: the serial controller supports slave mode only. any register can be addressed randomly. the address of the slave in the first 7 bits and the 8th bit tells whether the master is receiving data from the slave or transmitting data to the slave. the i 2 c write address is 0x6c and the read address is 0x6d. 4.2 slave mode protocol with reference to the clocking scheme shown in figure 5, the serial interface operates in the following manner: figure 5: serial interface slave mode protocol clock and data transitions: the sda pin is normally pulled high with an external device. data on the sda pin may change only during scl low time periods (see figure 6). data changes during scl high periods will indicate a start or stop condition as defined below. start condition: a high-to-low transition of sda with scl high is a start condition which must precede any other command (see figure 7). stop condition: a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the KT0806L in a standby power mode (see figure 7). acknowledge: all addresses and data words are serially transmitted to and from the KT0806L in 8- bit words. the KT0806L sends a ?0? to acknowledge that it has received each word. this happens during the ninth clock cycle (see figure 8).
copyright ? 2010, kt micro, inc. 6 KT0806L figure 6: clock and data transitions figure 7: start and stop definition figure 8: acknowledge
copyright ? 2010, kt micro, inc. 7 KT0806L 5 register bank the register bank stores channel frequency codes, calibration parameters, operation status, mode and power controls, which can be accessed by the internal digital controller, state machines and external micro controllers through the serial interface. all registers are 8 bits wide. control logics are active high unless specifically noted. register 7 6 5 4 3 2 1 0 0x00 chsel[8:1] 0x01 rfgain[1:0] pga[2:0] chsel[11:9] 0x02 chsel[0] rfgain[3] - - mute pltadj - phtcnst 0x04 alc_en mono pga_lsb[1:0] - - 0x0b standby - pdpa - - auto_pa dn - - 0x0c alc_decay_time[3:0] alc_attack_time[3:0] 0x0e - - - - - - pa_bias - 0x0f - - - pw_ok - slncid - - 0x10 - - - - - - pgamod 0x12 slncdis slncthl[2:0] slncthh[2:0] sw_mod 0x13 rfgain[2] - - - - pa_ctrl - - 0x14 slnctime[2:0] slnccnthigh[2:0] - slnctim e[3] 0x15 alccmpgain[2:0] 0x16 - - - slnccntlow[2:0] 0x17 - fdev au_enha nce xtal_se l 0x1e dclk xtald ref_clk[3:0] 0x26 alchold[2:0] alchighth[2:0] 0x27 alclowth[3:0] note 1: only read/write the defined registers. note 2: shaded registers are used in kt0806. 5.1 register 0x00 (address: 0x00, default value: 0x5c) bit 7 6 5 4 3 2 1 0 KT0806L chsel[8:1] please note that the default channel of KT0806L is 86mhz instead of 89.7mhz in kt0806 chsel[11:0] = dec2bin (target frequency in mhz x 20), where chsel[11:0] = reg0x1[2:0]:reg0x0[7:0]:reg0x2[7] 5.2 register 0x01 (address: 0x01, default value: 0xc3) bit 7 6 5 4 3 2 1 0 KT0806L rfgain[1:0] pga[2:0] chsel[11:9] bits type default label description 7:6 rw 11 rfgain[1:0] transmission range adjustment with rfgain[3] in reg 0x02[6] and rfgain[2] in reg 0x13[7] (see table 4 below)
copyright ? 2010, kt micro, inc. 8 KT0806L bits type default label description 5:3 rw 000 pga[2:0] pga gain control (see pga_lsb description, reg 0x04) 111: 12db 110: 8db 101: 4db 100: 0db 000: 0db 001: -4db 010: -8db 011: -12db 2:0 rw 011 chsel[11:9] fm channel selection[11:9] table 4: transmission power setting rfgain[3:0] rfout 0000 95.5 dbuv 0001 96.5 dbuv 0010 97.5 dbuv 0011 98.2 dbuv 0100 98.9 dbuv 0101 100 dbuv 0110 101.5 dbuv 0111 102.8 dbuv 1000 105.1 dbuv (107.2dbuv pa_bias=1) 1001 105.6 dbuv (108dbuv, pa_bias=1) 1010 106.2 dbuv (108.7dbuv, pa_bias=1) 1011 106.5 dbuv (109.5dbuv, pa_bias=1) 1100 107 dbuv (110.3dbuv, pa_bias=1) 1101 107.4 dbuv (111dbuv, pa_bias=1) 1110 107.7 dbuv (111.7dbuv, pa_bias=1) 1111 (default setting) 108 dbuv ( 112.5dbuv, pa_bias=1 ) 5.3 register 0x02 (address: 0x02, default: 0x40) bit 7 6 5 4 3 2 KT0806L chsel[0] rfgain[3] - - mute pltadj bits type default label description 7 rw 0 chsel[0] lsb of chsel 6 rw 1 rfgain[3] msb of rfgain 5:4 rw 00 reserved reserved 3 rw 0 mute software mute 0: mute disabled 1: mute enabled 2 rw 0 pltadj pilot tone amplitude adjustment 0: amplitude low 1: amplitude high 1 rw 0 reserved reserved 0 rw 0 phtcnst pre-emphasis time-constant set 0: 75 s (usa, japan) 1: 50 s (europe, australia)
copyright ? 2010, kt micro, inc. 9 KT0806L 5.4 register 0x04 (address: 0x04, default: 0x04) bit 7 6 5 4 3 2 1 0 KT0806L alc_en mono pga_lsb[1:0] - - kt0806 - mono pga_lsb[1:0] fdev[1:0] bass[1:0] bits type default label description 7 rw 0 alc_en automatic level control enable control 0 = disable alc 1 = enable alc 6 rw 0 mono force mono 0 = stereo 1 = mono 5:4 rw 00 pga_lsb[1:0] pga[2:0] pga_lsb[1:0] pga gain 111 11 12db 111 10 11 111 01 10 111 00 9 110 11 8 110 10 7 110 01 6 110 00 5 101 11 4 101 10 3 101 01 2 101 00 1 100 11 0 100 10 0 100 01 0 100 00 0 000 00 0 000 01 -1 000 10 -2 000 11 -3 001 00 -4 001 01 -5 001 10 -6 001 11 -7 010 00 -8 010 01 -9 010 10 -10 010 11 -11 011 00 -12 011 01 -13 011 10 -14 011 11 -15 3:2 rw 01 reserved reserved 1:0 rw 00 reserved reserved
copyright ? 2010, kt micro, inc. 10 KT0806L 5.5 register 0x0b (address: 0x0b, default: 0x00) bit 7 6 5 4 3 2 1 0 KT0806L standby - pdpa - - auto_padn - - kt0806 - - pdpa - - - - - bits type default label description 7 rw 0 standby chip standby control bit 0 = normal operation 1 = standby enable 6 rw 0 reserved reserved 5 rw 0 pdpa power amplifier power down 0 = power amplifier power on 1 = power amplifier power down 4 rw 0 reserved reserved 3 rw 0 reserved reserved 2 rw 0 auto_padn automatic power down power amplifier when silence is detected 0 = disable this feature 1 = enable this feature 1 rw 0 reserved reserved 0 rw 0 reserved reserved 5.6 register 0x0c (address: 0x0c, default: 0x00) - new bit 7 6 5 4 3 2 1 0 KT0806L alc_decay_time[3:0] alc_attack_time[3:0] kt0806 - - - - - - - - bits type default label description 7:4 rw 0000 alc_decay_time[ 3:0] alc decay time selection 0000 = 25us 0001 = 50us 0010 = 75us 0011 = 100us 0100 = 125us 0101 = 150us 0110 = 175us 0111 = 200us 1000 = 50ms 1001 = 100ms 1010 = 150ms 1011 = 200ms 1100 = 250ms 1101 = 300ms 1110 = 350ms 1111 = 400ms
copyright ? 2010, kt micro, inc. 11 KT0806L bits type default label description 3:0 rw 0000 alc_attack_tim e[3:0] alc attack time selection 0000 = 25us 0001 = 50us 0010 = 75us 0011 = 100us 0100 = 125us 0101 = 150us 0110 = 175us 0111 = 200us 1000 = 50ms 1001 = 100ms 1010 = 150ms 1011 = 200ms 1100 = 250ms 1101 = 300ms 1110 = 350ms 1111 = 400ms 5.7 register 0x0e (address: 0x0e, default: 0x02) bit 7 6 5 4 3 2 1 0 KT0806L - - - - - - pa_bias - bits type default label description 7:2 rw 0x00 reserved reserved 1 rw 1 pa_bias pa bias current enhancement. 0 = disable 1 = enable 0 rw 0 reserved reserved 5.8 register 0x0f (address: 0x0f, read only) bit 7 6 5 4 3 2 1 0 KT0806L - - - pw_ok - slncid - - bits type default label description 7 r na reserved reserved 6 r na reserved reserved 5 r na reserved reserved 4 r na pw_ok power ok indicator 3 r na reserved reserved 2 r na slncid 1 when silence is detected 1 r na reserved reserved 0 r na reserved reserved 5.9 register 0x10 (address: 0x10, default: 0xa8) bit 7 6 5 4 3 2 1 0 KT0806L - - - - - - - pgamod kt0806 - - - lmtlvl[1:0] - - pgamod
copyright ? 2010, kt micro, inc. 12 KT0806L bits type default label description 7:5 rw 101 reserved reserved 4:3 rw 01 reserved reserved 2:1 rw 00 reserved reserved 0 rw 0 pgamod pga mode selection 0 = 4db step 1 = 1db step with pga_lsb[1:0 ] used 5.10 register 0x12 (address: 0x12, default: 0x80) bit 7 6 5 4 3 2 1 0 KT0806L slncdis slncthl[2:0] slncthh[2:0] sw_mod bits type default label description 7 rw 1 slncdis silence detection disable 0 : enable 1 : disable 6:4 rw 000 slncthl silence detection low threshold 000 : 0.25mv 001 : 0.5mv 010 : 1mv 011 : 2mv 100 : 4mv 101 : 8mv 110 : 16mv 111 : 32mv 3:1 rw 000 slncthh silence detection high threshold 000 : 0.5mv 001 : 1mv 010 : 2mv 011 : 4mv 100 : 8mv 101 : 16mv 110 : 32mv 111 : 64mv 0 rw 0 sw_mod switching channel mode selection. 0 = mute when changing channel 1 = pa off when changing channel 5.11 register 0x13 (address: 0x13, default: 0x80) bit 7 6 5 4 3 2 1 0 KT0806L rfgain[2] - - pa_ctrl - - bits type default label description 7 rw 1 rfgain[2] pa (power amplifier) power (combined with reg 0x01[7:6] and reg 0x02[6])to set up transmission range) 6:3 rw 0000 reserved reserved
copyright ? 2010, kt micro, inc. 13 KT0806L bits type default label description 2 rw 0 pa_ctrl power amplifier structure selection 0 = internal power supply 1 = external power supply via external inductor note : when an external inductor is used, this bit must be set to 1 immediately after the power ok indicator reg 0x0f[4] is set to 1. otherwise, the device may be destroyed! 1:0 rw 00 reserved reserved 5.12 register 0x14 (address: 0x14, default 0x00) bit 7 6 5 4 3 2 1 0 KT0806L slnctime[2:0] slnccnthigh[2:0] - slnc_time[3] kt0806 slnctime[2:0] slnccnthigh[2:0] - - bits type default label description 7:5 rw 000 slnctime[2:0] silence detection low level and high level duration time 000 : 50ms (16s if slnctime[3] = 1) 001 : 100ms (24s if slnctime[3] = 1) 010 : 200ms (32s if slnctime[3] = 1) 011 : 400ms (40s if slnctime[3] = 1) 100 : 1s (48s if slnctime[3] = 1) 101 : 2s (56s if slnctime[3] = 1) 110 : 4s (60s if slnctime[3] = 1) 111 : 8s (64s if slnctime[3] = 1) 4:2 rw 000 slnccnthigh[2:0] silence detection high level counter threshold 000 : 15 001 : 31 010 : 63 011 : 127 100 : 255 101 : 511 110 : 1023 111 : 2047 1 rw 0 reserved reserved 0 rw 0 slnctime[3] silence detection long duration time enable 0 = short duration time enable 1 = long duration time enable 5.13 register 0x15 (address 0x15, default: 0xe0) - new bit 7 6 5 4 3 2 1 0 KT0806L alccmpgain[2:0] - - - kt0806 - - - bits type default label description
copyright ? 2010, kt micro, inc. 14 KT0806L bits type default label description 7:5 rw 111 alccmpgain[2:0] alc compressed gain setting 100 = 06 (6db) 101 = 03 (3db) 110 = 00 (0db) 111= 1d (-3db) 000 = 1a(-6db) 001 = 17(-9db) 010 = 14(-12db) 011 = 11(-15db) 4:0 r 0000 reserved reserved 5.14 register 0x16 (address 0x16, default: 0x00) bit 7 6 5 4 3 2 1 0 KT0806L - - - slnccntlow[2:0] bits type default label description 7:3 rw 0x0 reserved reserved 2:0 rw 000 slnccntlow[2:0] silence low counter 000 : 1 001 : 2 010 : 4 011 : 8 100 : 16 101 : 32 110 : 64 111 : 128 5.15 register 0x17 (address 0x17, default: 0x00) - new bit 7 6 5 4 3 2 1 0 KT0806L - fdev au_enhance - xtal_sel kt0806 - - - bits type default label description 7 rw 0 reserved reserved 6 rw 0 fdev frequency deviation selection 0 = 75khz deviation 1 = 112.5khz deviation 5 rw 0 au_enhance audio frequency response enhancement enable 0 = disable 1 = enable 4 rw 0 reserved reserved 3 rw 0 xtal_sel software controlled crystal oscillator selection 0 = 32.768khz crystal 1 = 7.6mhz crystal 5.16 register 0x1e (address 0x1e, default: 0x00) - new bit 7 6 5 4 3 2 1 0 KT0806L - dclk xtald - ref_clk<3:0> kt0806 - - -
copyright ? 2010, kt micro, inc. 15 KT0806L bits type default label description 7 rw 0 reserved reserved 6 rw 0 dclk multiple reference clock selection enable 0 = disable multiple reference clock feature and reference clock or crystal oscillator can only select through sw1/sw2 pins. 1 = enable multiple reference clock and user can select different reference clock through ref_clk[3:0] 5 rw 0 xtald crystal oscillator disable control 0 = enable crystal oscillator 1 = disable crystal oscillator 4 rw 0 reserved reserved 3:0 rw 0000 ref_clk[3:0] reference clock selection 0000 = 32.768khz 0001 = 6.5mhz 0010 = 7.6mhz 0011 = 12mhz 0100 = 13mhz 0101 = 15.2mhz 0110 = 19.2mhz 0111 = 24mhz 1000 = 26mhz others = reserved 5.17 register 0x26 (address 0x26, default: 0xa0) - new bit 7 6 5 4 3 2 1 0 KT0806L alchold[2:0] - alchighth[2:0] - kt0806 - - - bits type default label description 7:5 rw 101 alchold[2:0] alc hold time selection 000 = 50ms 001 = 100ms 010 = 150ms 011 = 200ms 100 = 1s 101 = 5s 110 = 10s 111 = 15s 4 rw 0 reserved reserved 3:1 rw 000 alchighth[2:0] alc high threshold selection 000 = 0.6 001 = 0.5 010 = 0.4 011 = 0.3 100 = 0.2 101 = 0.1 110 = 0.05 111 = 0.01 0 rw 0 reserved reserved
copyright ? 2010, kt micro, inc. 16 KT0806L 5.18 register 0x27 (address 0x27, default: 0x00) - new bit 7 6 5 4 3 2 1 0 KT0806L - - - - alclowth[3:0] kt0806 - - - bits type default label description 7:4 rw 0000 reserved reserved 3:0 rw 0000 alclowth[3:0] alc low threshold 0000 = 0.25 0001 = 0.2 0010 = 0.15 0011 = 0.1 0100 = 0.05 0101 = 0.03 0110 = 0.02 0111 = 0.01 1000 = 0.005 1001 = 0.001 1010 = 0.0005 1011 = 0.0001 others = reserved
copyright ? 2010, kt micro, inc. 17 KT0806L 6 chip enable and mode control there are three pins sw1/sw2 to enable the chip and determine the reference clock or crystal. the definition is shown below. table 5: pin sw1/sw2 sw1 sw2 chip mode iovdd clock source 0 0 power off 1.6~3.6v n/a 0 1 power on 1.6~3.6v 12mhz 1 0 power on 1.6~3.6v 32.768khz 1 1 power on 1.6~3.6v 7.6mhz 7 mute the fm transmitter can be muted by setting register mute to ?1? through i2c programming. 8 silence detection bit name register location description slncdis reg 0x12[7] setting to 0 to enable the silence detection. slnctime[2:0] reg 0x14[7:5] silence detection time window. slnctime[3] reg 0x14[0] silence detection long time window. slncthl[2:0] reg 0x12[6:4] low threshold voltage of input signal for silence detection. slncthh[2:0] reg 0x12[3:1] high threshold voltage of input signal for silence detection. slnccnthigh [2:0] reg 0x14[4:2] # of time when the input signal amplitude is higher than slncthh[2:0]. slnccntlow [2:0] reg 0x16[2:0] # of time when the input signal amplitude is lower than slncthl[2:0]. slncid reg 0x0f[2] (read only) set to 1 when silence is detected. the silence detection scheme is enabled by setting slncdis to 0. during the time defined by slntime[2:0], the chip will be muted when the number of time when the input amplitude is higher than the voltage defined by slncthl[2:0] is lower than slnccntlow [2:0]. the slncid bit is set to 0. in KT0806L, slnctime[3] is added to increase the silence time, which allow user set the silence time up to 64s. another enhanced feature is that KT0806L can power down power amplifier automatically if the silence time meet the specified value by setting auto_padn to 1. when the input signal amplitude is higher than the voltage defined by slncthh[2:0] and the number of time when that happens is more than slnccnthigh [2:0], the chip exits from the mute status and the slncid is cleared to 0.
copyright ? 2010, kt micro, inc. 18 KT0806L 9 alc (automatic level control) figure 9 alc working principle bit name register location description alc_decay_time[3:0] reg0x0c[7:4] alc decay time alc_attack_time[3:0] reg0x0c[3:0] alc attack time alchold[2:0] reg0x26[7:5] alc hold time alchighth[2:0] reg0x26[3:1] alc high threshold level alclowth[3:0] reg0x27[3:0] alc low threshold level alccmpgain[2:0] reg0x15[7:5] alc compressed gain alc_en reg0x04[7] alc enable control alc is used to control the audio gain automatically according to the amplitude of the current input signal as shown in figure 9. once the signal higher than the value specified in register alchighth[2:0] is detected, the audio gain will be compressed to the value specified in register alccmpgain[2:0] automatically. the time used to decrease from current audio gain to compressed audio gain is called decay time and can be specified through register alc_decay_time[3:0]. if all the signal level are below the value specified in register alclowth[3:0] within a certain time(this time is called hold time and can be specified through register alchold[2:0]), the audio will be increase from the compressed gain to original gain. the gain rising time is called attack time and this time can also be specified in register alc_attack_time[3:0]. 10 reset the global reset is issued after automatic on-chip power-on reset. after a global reset, all registers are reset to the default value.
copyright ? 2010, kt micro, inc. 19 KT0806L 11 typical application circuits the KT0806L can be integrated in a wide range of systems by requiring only a single power supply. figure 10 shows the external diagram for the drop-in replacement of kt0806. u1 KT0806L iovdd 16 nc 1 inl 2 gnd 3 inr 4 nc1 5 nc2 6 sw1 7 sw2 8 gnd 9 sda 10 scl 11 pa_out 12 gnd 13 xo 14 xi/clk 15 antenna c1 15pf c2 15pf y1 32.768khz xo xi optional v3.3 c3 0.1uf v3.3 sw1 sda scl c4 0.1uf c5 0.1uf r l figure 10: typical configuration for a drop-in replacement of kt0806 as shown in the block above, KT0806L is fully compatible with kt0806. components value/description suppliers c1,c2 capacitor, 15pf c3 supply decoupling capacitor, 0.1uf must be as close to chip as possible c4,c5 ac decoupling capacitor, 0.1uf (optional) y1 crystal, 32.768khz
copyright ? 2010, kt micro, inc. 20 KT0806L u1 KT0806L iovdd 16 nc 1 inl 2 gnd 3 inr 4 nc1 5 nc2 6 sw1 7 sw2 8 gnd 9 sda 10 scl 11 pa_out 12 gnd 13 xo 14 xi/clk 15 antenna optional l1 100nh v3.3 v3.3 c1 0.1uf rclk v3.3 sw1 sda scl c2 0.1uf c3 0.1uf r l figure 11: application that requires higher transmission power (>5dbm) components value/description suppliers c1 supply decoupling capacitor, 0.1uf must be as close to chip as possible c2,c3 ac decoupling capacitor, 0.1uf (optional) l1 inductor, 100nh
copyright ? 2010, kt micro, inc. 21 KT0806L 12 package outline dimensions in millimeters dimensions in inches symbol min. max. min. max. a 0.700/0.800 0.800/0.900 0.028/0.031 0.031/0.035 a1 0.000 0.050 0.000 0.002 a3 0.203ref. 0.008ref. d 2.900 3.100 0.114 0.122 e 2.900 3.100 0.114 0.122 d1 1.600 1.800 0.063 0.071 e1 1.600 1.800 0.063 0.071 k 0.200min. 0.008min. b 0.180 0.300 0.007 0.012 e 0.500typ. 0.020typ. l 0.300 0.500 0.012 0.020
copyright ? 2010, kt micro, inc. 22 KT0806L 13 order information part number description package KT0806L 3 rd gen monolithic digital stereo fm transmitter qfn 3x3 16, pb free, 5000 pcs per reel 14 revision history v1.0 official release v1.1 deleted ?gpio[1:0]? register. v1.2 modified table 3, figure 2, figure 10, figure 11 and section 8. v1.3 modified table 1 and table 2. v1.4 modified register bank.
copyright ? 2010, kt micro, inc. 23 KT0806L 15 contact information kt micro, inc. 999 corporate drive, suite 170 ladera ranch, ca 92694 usa tel: 949-713-4000 fax: 949-713-4004 email: sales@ktmicro.com ??? ?j 2 ??? 2 b 8 (100097) 8610-88891945 8610-88891977 ? sales@ktmicro.com ? http://www.ktmicro.com.cn

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